Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Via placement for slim border electro-optic display backplanes with decreased capacitive coupling between t-wires and pixel electrodes

Via placement for slim border electro-optic display backplanes with decreased capacitive coupling between t-wires and pixel electrodes

US Patent 11081066 · Granted Aug 3, 2021

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electro-optic displays and methods for driving the same2025
Staged gate voltage control2025
Methods for driving electro-optic displays2025
Time-shifted waveforms for multi-particle electrophoretic displays providing low2025
Time-shifted waveforms for multi-particle electrophoretic displays providing low2025
Electro-optic displays and methods for discharging remnant voltage using backlig2025
Electro-optic displays and driving methods2025
Electro-optic displays and driving methods2025
Methods for globally applying voltages to the display pixels of electro-optic di2025
Layered structure with high dielectric constant for use with active matrix backp2025
Methods for measuring electrical properties of electro-optic displays2025
Methods for measuring electrical properties of electro-optic displays2025