Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Block-on-block memory array architecture using bi-directional staircases

Block-on-block memory array architecture using bi-directional staircases

US Patent 10978478 · Granted Apr 13, 2021

Estimated economic value: $23,307,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Independent plane architecture in a memory device2025
3D memory device including shared select gate connections between memory blocks2024
Devices including stair step structures, and related memory devices and electron2024
Block-on-block memory array architecture using bi-directional staircases2024
Using non-segregated cells as drain-side select gates for sub-blocks in a memory2024
Reducing programming disturbance in memory devices2024
Microelectronic devices including control logic regions2024
Microelectronic devices having a memory array region, a control logic region, an2024
Memory devices with four data line bias levels2024
Vertical string driver for memory array2023
Reducing programming disturbance in memory devices2023
3D memory device including shared select gate connections between memory blocks2023