Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Sequential error capture during memory test

Sequential error capture during memory test

US Patent 10971242 · Granted Apr 6, 2021

Estimated economic value: $3,234,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System testing using partitioned and controlled noise2024
Method to limit the time a semiconductor device operates above a maximum operati2023
Testing bit write operation to a memory array in integrated circuits2023
Testing bit write operation to a memory array in integrated circuits2023
Microchip level shared array repair2022
Microchip level shared array repair2022
Tunable power save loop for processor chips2021
Built-in self-test for bit-write enabled memory arrays2021
Built-in self-test for bit-write enabled memory arrays2021
Built-in self-test for bit-write enabled memory arrays2021
Implementing dynamic SEU detection and correction method and circuit2021
Implementing SEU detection method and circuit2021