Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same

Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same

US Patent 10957680 · Granted Mar 23, 2021

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Three-dimensional memory device with laterally separated source select electrode2025
Current source for read of programmable resistance memory cells2025
Select gate bias gradation structure in NAND memory2025
Sub-block separation in NAND memory through word line based selectors2025
Bonded assembly containing conductive via structures extending through word line2025
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2025
Three-dimensional memory device and method of making thereof using double pitch 2025
Three-dimensional memory device containing plural metal oxide blocking dielectri2025
Three-dimensional memory device containing epitaxial pedestals and top source co2025
Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensio2025
Quasi-volatile memory with reference bit line structure2025
Overwrite read methods for resistance switching memory devices2025