Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Techniques for pre-silicon testing integrated circuit designs that accommodate power-supply noise and adaptive-clock aware timing

Techniques for pre-silicon testing integrated circuit designs that accommodate power-supply noise and adaptive-clock aware timing

US Patent 10929591 · Granted Feb 23, 2021

Estimated economic value: $602,809,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Technique for enabling on-die noise measurement during ate testing and IST2025
Low power and area clock monitoring circuit using ring delay arrangement for clo2025
Detection of electromagnetic fault injection attacks on digital systems2025
On die current sink circuit for overshoot mitigation2025
Integrated current monitor2025
Integrated current monitor using variable drain-to-source voltages2025
Squelch detection device2025
Transient current-mode signaling scheme for on-chip interconnect fabrics2025
Overvoltage and undervoltage detector2025
Low power and area clock monitoring circuit using a capacitor and constant curre2025
Nested query modification tool2025
Visualization tool for building nested queries2025