Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Low latency data transfer technique for mesochronous divided clocks

Low latency data transfer technique for mesochronous divided clocks

US Patent 10623174 · Granted Apr 14, 2020

Estimated economic value: $21,268,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Measuring and compensating for clock tree variation2025
Low latency phase alignment for parallel data paths2025
Deterministic reset mechanism for asynchronous gearbox FIFOs for predictable lat2025
Deterministic reset mechanism for asynchronous gearbox FIFOs for predictable lat2025
Configurable testing of semiconductor devices2023
Configurable testing of semiconductor devices2023
Serial lane-to-lane skew reduction2022
Serial lane-to-lane skew reduction2022
Circuit and method for dynamic clock skew compensation2021
Circuit and method for dynamic clock skew compensation2021
Circuit for and method of providing a programmable connector of an integrated ci2020
Circuit for and method of providing a programmable connector of an integrated ci2020