Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Code sequencer that, in response to a primary processing unit encountering a trigger instruction, receives a thread identifier, executes predefined instruction sequences, and offloads computations to at least one accelerator

Code sequencer that, in response to a primary processing unit encountering a trigger instruction, receives a thread identifier, executes predefined instruction sequences, and offloads computations to at least one accelerator

US Patent 10599441 · Granted Mar 24, 2020

Estimated economic value: $7,005,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Duplicate write circuit2025
Network device with datagram transport layer security selective software offload2025
Flexible cryptographic architecture in a network device2025
Maintaining data confidentiality in shared computing environments2025
Network device with programmable action processing2025
Confidential computing with device memory isolation2025
Efficient montgomery multiplier2024
Fast precomputation for Montgomery multiplier2024
Network adapter with efficient storage-protocol emulation2023
Timing-adaptive, configurable logic architecture2020