Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Logic buffer for hitless single event upset handling

Logic buffer for hitless single event upset handling

US Patent 10565048 · Granted Feb 18, 2020

Estimated economic value: $159,836,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High-speed DIMM slot terminator2025
Back-side wafer modification2023
Method to limit the time a semiconductor device operates above a maximum operati2023
Regenerative power-over-ethernet (PoE) mid-span injector2022
Low temperature threshold fan gating2022
Downstream slack creation in integrated circuit development2021
Logic buffer for hitless single event upset handling2021
Logic buffer for hitless single event upset handling2021
Logic buffer for hitless single event upset handling2021
Progressive latch for electrical module2021
High-potential testing of conductive lands of a printed circuit board2021
Fan with EMI absorbent blades2020