Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of creating aligned vias in ultra-high density integrated circuits

Method of creating aligned vias in ultra-high density integrated circuits

US Patent 10522394 · Granted Dec 31, 2019

Estimated economic value: $20,765,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Continuous time linear equalizers (CTLEs) of data interfaces2025
Double seal ring and electrical connection of multiple chiplets2025
Gate stack for metal gate transistor2025
Power consumption control for transmitters of retimers in high speed data commun2025
Performance of magnetic channel junctions2025
Voltage regulation for multiple voltage levels2024
Electronic fuse (eFuse) designs for enhanced chip security2024
Three-dimensional flash memory device with increased storage density2024
Leakage detection for three-dimensional NAND memory2024
Gate stack for metal gate transistor2024
Voltage regulation for multiple voltage levels2023
Real-time, in-situ reliability monitoring in an integrated circuit2023