Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Heterojunction semiconductor device for reducing parasitic capacitance

Heterojunction semiconductor device for reducing parasitic capacitance

US Patent 10468516 · Granted Nov 5, 2019

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor device including source pad region and drain pad region configured2024
Semiconductor device including source pad region and drain pad region configured2024
Counter-balanced mobile device and crane2024
Semiconductor device having reduced capacitance between source and drain pads2023
Semiconductor device having reduced capacitance between source and drain pads2023
Device and semiconductor structure for improving the disadvantages of p-GaN gate2022
Electrical connector assembly having floating heat sink in resilient manner2022
Semiconductor device manufacturing method2022
Power-measuring protection method and laser protection system2022
Enclosed gate runner for eliminating miller turn-on2021
Lateral power device with reduced on-resistance2021
Electrical connector with therein embedded grounding bar secured by conductive a2021