{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies", "item": "https://www.patentleaderboard.com/patent/10387037"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies

Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies

US Patent 10387037 · Granted Aug 20, 2019

Estimated economic value: $17,708,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Machine learning accelerator mechanism2025
Machine learning sparse computation mechanism for arbitrary neural networks, ari2025
Systems, methods, and apparatuses for heterogeneous computing2024
Systems, methods, and apparatuses for heterogeneous computing2024
Holographic calling for artificial reality2024
Machine learning accelerator mechanism2024
Machine learning sparse computation mechanism for arbitrary neural networks, ari2024
Dynamic content rendering based on context for AR and assistant systems2024
Systems and methods for reading and writing sparse data in a neural network acce2024
Spatial tiling of compute arrays with shared control2024
Tensor controller architecture2024
Systems and methods for speech or text processing using matrix operations2024