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Home › Low distortion sample and hold (S/H) circuits and associated methods for use with analog-to-digital converters (ADCs)

Low distortion sample and hold (S/H) circuits and associated methods for use with analog-to-digital converters (ADCs)

US Patent 10354741 · Granted Jul 16, 2019

Estimated economic value: $5,481,000 ⓘ

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