Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Non-volatile memory sub-block erasure disturb management scheme

Non-volatile memory sub-block erasure disturb management scheme

US Patent 10354737 · Granted Jul 16, 2019

Estimated economic value: $31,954,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Protective case for index controllers2025
Storing log and user data in SSD with independent plane operations2024
Wear leveling methods for zoned namespace solid state drive2022
Bounded latency and command non service methods and apparatus2021
Flash memory polling2021
Bounded latency and command non service methods and apparatus2020
Soft information module2019
Reduced complexity non-binary LDPC decoding algorithm2019
Error correcting code adjustment for a data storage device2018
System and method for utilizing history information in a memory device2018
Data retention in a memory block based on local heating2018
Non-volatile memory with dynamic repurpose of word line2018