Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Phase lock loop bypass for board-level testing of systems

Phase lock loop bypass for board-level testing of systems

US Patent 10303237 · Granted May 28, 2019

Estimated economic value: $17,387,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System, method, apparatus and architecture for dynamically configuring device fa2025
Low latency communication path for audio/visual (A/V) applications2025
Interconnect network for multi-tile system on chips2025
System-on-a-chip (SoC) architecture for low power state communication2025
Atomic handling for disaggregated 3D structured SoCs2025
Infrastructure for platform immersive experience2025
Dynamic voltage and frequency scaling for discrete graphics systems2025
Methods and apparatus to reduce display connection latency2024
System, apparatus and method for functional testing of one or more fabrics of a 2023
System, apparatus and method for providing a fabric for an accelerator2022
System, apparatus and method for inter-die functional testing of an integrated c2021
Dynamically programmable memory test traffic router2021