Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Read latency reduction in a memory device

Read latency reduction in a memory device

US Patent 10290334 · Granted May 14, 2019

Estimated economic value: $3,106,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Low power standby mode for memory devices2025
Low power standby mode for memory devices2025
Integrated module assembly for optical integrated circuits2024
Latency reduction in SPI flash memory devices2023
Standby current reduction in memory devices2023
Memory latency reduction in XIP mode2022
Memory latency reduction in XIP mode2022
Concurrent read and reconfigured write operations in a memory device2021
Concurrent read and reconfigured write operations in a memory device2021
Reference circuits and methods for resistive memories2021
Read latency reduction in a memory device2020
Read latency reduction in a memory device2020