Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory capable of entering/exiting power down state during self-refresh period and associated memory controller and memory system

Memory capable of entering/exiting power down state during self-refresh period and associated memory controller and memory system

US Patent 10109341 · Granted Oct 23, 2018

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor structure and semiconductor device2025
Electronic system and method for controlling burst length to access memory devic2025
DRAM, memory controller and associated training method2023
DRAM, memory controller and associated training method2023
Delay tracking method and memory system2022
DRAM, memory controller and associated training method2021
DRAM, memory controller and associated training method2021
Delay tracking method and memory system2021
Semiconductor devices and methods for enhancing signal integrity of an interface2021
Refresh control method for memory system to perform refresh action on all memory2020
Memory device, memory controller and associated memory system operated according2020
Memory device, memory controller and associated memory system operated according2020