Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same

Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same

US Patent 10079185 · Granted Sep 18, 2018

Estimated economic value: $224,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multi-stimulation neurorehabilitation assistant system2025
Web page access system and web page access method2025
Security lock2025
Metal gate structure and method of forming the same2025
Graphics card lifting device2025
Semiconductor structure2025
Locking method for an electronic device and electronic device locking apparatus2025
Semiconductor device with a work function layer having an oxygen-blocking dopant2025
Controller2025
Stepless adjustable electronic device locking apparatus2025
Water carrier2025
Semiconductor device and method of manufacture2025