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Home › Semiconductor integrated circuit device having enhancement type NMOS and depression type MOS with N-type channel impurity region and P-type impurity layer under N-type channel impurity region

Semiconductor integrated circuit device having enhancement type NMOS and depression type MOS with N-type channel impurity region and P-type impurity layer under N-type channel impurity region

US Patent 10014294 · Granted Jul 3, 2018

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