Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9170841 | Multiprocessor system for comparing execution order of tasks to a failure pattern | Kiyokazu Fukuzaki, Masanori Henmi, Hiroyuki Murata, Takatsugu Sawai, Hiroyuki Shigeta | 2015-10-27 |
| 7970998 | Parallel caches operating in exclusive address ranges | Takao Yamamoto, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko | 2011-06-28 |
| 7953935 | Cache memory system, and control method therefor | Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko | 2011-05-31 |
| 7594099 | Processor executing SIMD instructions | Tetsuya Tanaka, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara +3 more | 2009-09-22 |
| 7555610 | Cache memory and control method thereof | Ryuta Nakanishi, Tetsuya Tanaka | 2009-06-30 |
| 7502887 | N-way set associative cache memory and control method thereof | Tetsuya Tanaka, Ryuta Nakanishi, Tokuzo Kiyohara, Takao Yamamoto, Keisuke Kaneko | 2009-03-10 |
| 7454575 | Cache memory and its controlling method | Ryuta Nakanishi, Tetsuya Tanaka, Shuji Miyasaka | 2008-11-18 |
| 7380112 | Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags | Tetsuya Tanaka, Taketo Heishi, Hajime Ogawa | 2008-05-27 |
| 7281117 | Processor executing SIMD instructions | Tetsuya Tanaka, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara +3 more | 2007-10-09 |
| 7185176 | Processor executing SIMD instructions | Tetsuya Tanaka, Taketo Heishi, Hajime Ogawa, Yoshihiro Koga, Manabu Kuroda +5 more | 2007-02-27 |