Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7124319 | Delay compensation for synchronous processing sets | John E. Watkins, Paul J. Garnett | 2006-10-17 |
| 7099984 | Method and system for handling interrupts and other communications in the presence of multiple processing sets | John E. Watkins, Paul J. Garnett | 2006-08-29 |
| 6961826 | Processor state reintegration using bridge direct memory access controller | Paul J. Garnett, Jeremy Harris | 2005-11-01 |
| 6587961 | Multi-processor system bridge with controlled access | Paul J. Garnett, Femi A. Oyelakin | 2003-07-01 |
| 6260159 | Tracking memory page modification in a bridge for a multi-processor system | Paul J. Garnett, Femi A. Oyelakin | 2001-07-10 |
| 6223230 | Direct memory access in a bridge for a multi-processor system | Paul J. Garnett, Femi A. Oyelakin | 2001-04-24 |
| 6173351 | Multi-processor system bridge | Paul J. Garnett, Femi A. Oyelakin | 2001-01-09 |
| 6167477 | Computer system bridge employing a resource control mechanism with programmable registers to control resource allocation | Paul J. Garnett, Femi A. Oyelakin, Emrys J. Williams | 2000-12-26 |
| 6148348 | Bridge interfacing two processing sets operating in a lockstep mode and having a posted write buffer storing write operations upon detection of a lockstep error | Paul J. Garnett, Femi A. Oyelakin | 2000-11-14 |
| 6141718 | Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data direct memory accesses | Paul J. Garnett, Femi A. Oyelakin | 2000-10-31 |
| 6138198 | Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data write accesses | Paul J. Garnett, Femi A. Oyelakin, Emrys J. Williams | 2000-10-24 |