Issued Patents All Time
Showing 126–150 of 163 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6812046 | Method and apparatus for electronically aligning capacitively coupled chip pads | Ivan E. Sutherland, Gregory M. Papadopoulos | 2004-11-02 |
| 6768195 | Multi-chip semiconductor device | — | 2004-07-27 |
| 6753726 | Apparatus and method for an offset-correcting sense amplifier | Ivan E. Sutherland | 2004-06-22 |
| 6738415 | Bi-directional communication system | Robert J. Bosnyak | 2004-05-18 |
| 6710436 | Method and apparatus for electrostatically aligning integrated circuits | David L. Harris, Ivan E. Sutherland | 2004-03-23 |
| 6696876 | Clock interpolation through capacitive weighting | Robert J. Bosnyak | 2004-02-24 |
| 6526552 | Long line receiver for CMOS integrated circuits | Robert J. Bosnyak, Jose M. Cruz | 2003-02-25 |
| 6509765 | Selectable resistor and/or driver for an integrated circuit with a linear resistance | — | 2003-01-21 |
| 6495396 | Method of coupling and aligning semiconductor devices including multi-chip semiconductor devices | — | 2002-12-17 |
| 6472931 | Method and apparatus that models neural transmission to amplify a capacitively-coupled input signal | Sharon Sookdeo-Drost | 2002-10-29 |
| 6396308 | Sense amplifier with dual linearly weighted inputs and offset voltage correction | Robert J. Bosnyak | 2002-05-28 |
| 6384642 | Switched positive feedback for controlled receiver impedance | Robert J. Bosnyak, Jose M. Cruz | 2002-05-07 |
| 6373304 | Techniques for making and using an improved loop filter which maintains a constant zero frequency to bandwidth ratio | Robert J. Bosnyak, Jose M. Cruz | 2002-04-16 |
| 6329836 | Resistive arrayed high speed output driver with pre-distortion | Robert J. Bosnyak | 2001-12-11 |
| 6304098 | Method and apparatus for reducing noise in communication channels having a shared reference signal | Neil C. Wilhelm | 2001-10-16 |
| 6194929 | Delay locking using multiple control signals | Jose M. Cruz, Robert J. Bosnyak | 2001-02-27 |
| 6148038 | Circuit for detecting and decoding phase encoded digital serial data | Robert J. Bosnyak | 2000-11-14 |
| 6084452 | Clock duty cycle control technique | Jose M. Cruz, Robert J. Bosnyak | 2000-07-04 |
| 6076175 | Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits | Robert J. Bosnyak | 2000-06-13 |
| 6055269 | Adaptive equalization technique using twice sampled non-return to zero data | Robert J. Bosnyak, Jose M. Cruz | 2000-04-25 |
| 6031406 | Single rail regulator | Robert J. Bosnyak, Jose M. Cruz | 2000-02-29 |
| 6028903 | Delay lock loop with transition recycling for clock recovery of NRZ run-length encoded serial data signals | Robert J. Bosnyak | 2000-02-22 |
| 6020765 | Frequency difference detector for use with an NRZ signal | Robert J. Bosnyak | 2000-02-01 |
| 6016082 | Low phase noise LC oscillator for microprocessor clock distribution | Jose M. Cruz, Robert J. Bosnyak | 2000-01-18 |
| 5982834 | Clock recovery system for high speed small amplitude data stream | Robert J. Bosnyak | 1999-11-09 |