Issued Patents All Time
Showing 126–138 of 138 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6453440 | System and method for detecting double-bit errors and for correcting errors due to component failures | — | 2002-09-17 |
| 6393597 | Mechanism for decoding linearly-shifted codes to facilitate correction of bit errors due to component failures | — | 2002-05-21 |
| 6304992 | Technique for correcting single-bit errors in caches with sub-block parity bits | — | 2001-10-16 |
| 6301680 | Technique for correcting single-bit errors and detecting paired double-bit errors | — | 2001-10-09 |
| 6289420 | System and method for increasing the snoop bandwidth to cache tags in a multiport cache memory subsystem | — | 2001-09-11 |
| 6282686 | Technique for sharing parity over multiple single-error correcting code words | — | 2001-08-28 |
| 6233716 | Technique for partitioning data to correct memory part failures | — | 2001-05-15 |
| 6141789 | Technique for detecting memory part failures and single, double, and triple bit errors | — | 2000-10-31 |
| 5513313 | Method for generating hierarchical fault-tolerant mesh architectures | Jehoshua Bruck, Ching-Tien Ho | 1996-04-30 |
| 5513371 | Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressible nodes based on address bit permutations | Jorge L. C. Sanz | 1996-04-30 |
| 5444701 | Method of packet routing in torus networks with two buffers per edge | Luis Gravano | 1995-08-22 |
| 5280607 | Method and apparatus for tolerating faults in mesh architectures | Jehoshua Bruck, Ching-Thien Ho | 1994-01-18 |
| 5271014 | Method and apparatus for a fault-tolerant mesh with spare nodes | Jehoshua Bruck, Ching-Tien Ho | 1993-12-14 |