Issued Patents All Time
Showing 51–75 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9417910 | System and method for implementing shared probabilistic counters storing update probability values | Yosef Lev, Mark S. Moir | 2016-08-16 |
| 9367363 | System and method for integrating best effort hardware mechanisms for supporting transactional memory | Mark S. Moir | 2016-06-14 |
| 9342380 | System and method for implementing reader-writer locks using hardware transactional memory | Yosef Lev, Yujie Liu, Victor M. Luchangco, Mark S. Moir | 2016-05-17 |
| 9304776 | System and method for mitigating the impact of branch misprediction when exiting spin loops | Mark S. Moir | 2016-04-05 |
| 9208081 | Concurrent object management | Nir N. Shavit, Mark S. Moir, Antonios Printezis | 2015-12-08 |
| 9183043 | Systems and methods for adaptive integration of hardware and software lock elision techniques | Alex Kogan, Yosef Lev, Timothy Merrifield, Mark S. Moir | 2015-11-10 |
| 9183048 | System and method for implementing scalable contention-adaptive statistics counters | Yosef Lev, Mark S. Moir | 2015-11-10 |
| 9158596 | Partitioned ticket locks with semi-local spinning | — | 2015-10-13 |
| 9110718 | Supporting targeted stores in a shared-memory multiprocessor system | Mark S. Moir, Paul N. Loewenstein | 2015-08-18 |
| 9021502 | Method and system for inter-thread communication using processor messaging | Mark S. Moir | 2015-04-28 |
| 8990503 | Monitoring multiple memory locations for targeted stores in a shared-memory multiprocessor | Mark S. Moir, Paul N. Loewenstein | 2015-03-24 |
| 8973004 | Transactional locking with read-write locks in transactional memory systems | Nir N. Shavit | 2015-03-03 |
| 8966491 | System and method for implementing NUMA-aware reader-writer locks | Irina Calciu, Victor M. Luchangco, Virendra J. Marathe, Nir N. Shavit, Yosef Lev | 2015-02-24 |
| 8918596 | System and method for implementing NUMA-aware statistics counters | Yosef Lev, Mark S. Moir | 2014-12-23 |
| 8914620 | Method and system for reducing abort rates in speculative lock elision using contention management mechanisms | — | 2014-12-16 |
| 8909601 | System and method for implementing shared scalable nonzero indicators | Mark S. Moir, Yosef Lev, Victor M. Luchangco | 2014-12-09 |
| 8826249 | Method and system for optimizing code for a multi-threaded application | Virendra J. Marathe, Mark S. Moir | 2014-09-02 |
| 8789057 | System and method for reducing serialization in transactional memory using gang release of blocked threads | Mark S. Moir | 2014-07-22 |
| 8775837 | System and method for enabling turbo mode in a processor | Nir N. Shavit, Virendra J. Marathe | 2014-07-08 |
| 8776063 | Method and system for hardware feedback in transactional memory | Kevin Moore, Mark S. Moir | 2014-07-08 |
| 8732682 | Systems and methods for detecting and tolerating atomicity violations between concurrent code blocks | Virendra J. Marathe | 2014-05-20 |
| 8725974 | Page-protection based memory access barrier traps | Antonios Printezis | 2014-05-13 |
| 8707006 | Cache index coloring for virtual-address dynamic allocators | — | 2014-04-22 |
| 8694706 | System and method for NUMA-aware locking using lock cohorts | Virendra J. Marathe, Nir N. Shavit | 2014-04-08 |
| 8689237 | Multi-lane concurrent bag for facilitating inter-thread communication | Oleksandr Otenko | 2014-04-01 |