Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7227869 | Serial media independent interface | Stewart Findlater | 2007-06-05 |
| 7218632 | Packet processing engine architecture | David R. Cheriton | 2007-05-15 |
| 7215641 | Per-flow dynamic buffer management | David R. Cheriton | 2007-05-08 |
| 7043541 | Method and system for providing operations, administration, and maintenance capabilities in packet over optics networks | Hiroshi Suzuki, Marinica Rusu, Paul James Frantz, Sharat Prasad | 2006-05-09 |
| 7023853 | Access control list processing in hardware | David R. Cheriton | 2006-04-04 |
| 6956852 | Multi-function high-speed network interface | Howard Frazier, Thomas J. Edsall | 2005-10-18 |
| 6829217 | Per-flow dynamic buffer management | David R. Cheriton | 2004-12-07 |
| 6798776 | Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network | David R. Cheriton | 2004-09-28 |
| 6738862 | Block mask ternary CAM | Mark A. Ross | 2004-05-18 |
| 6658002 | Logical operation unit for packet processing | Mark A. Ross, Sun Den Chen | 2003-12-02 |
| 6515963 | Per-flow dynamic buffer management | David R. Cheriton | 2003-02-04 |
| 6389506 | Block mask ternary cam | Mark A. Ross | 2002-05-14 |
| 6385208 | Serial media independent interface | Stewart Findlater | 2002-05-07 |
| 6377577 | Access control list processing in hardware | David R. Cheriton | 2002-04-23 |
| 6343072 | Single-chip architecture for shared-memory router | David R. Cheriton | 2002-01-29 |
| 6091725 | Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network | David R. Cheriton | 2000-07-18 |
| 5973951 | Single in-line memory module | Edward H. Frank, James Testa, Shawn Storm | 1999-10-26 |
| 5764935 | High speed active bus | Timothy Bucher, Edmund J. Kelly | 1998-06-09 |
| 5532954 | Single in-line memory module | Edward H. Frank, James Testa, Shawn Storm | 1996-07-02 |
| 5465229 | Single in-line memory module | Edward H. Frank, James Testa, Shawn Storm | 1995-11-07 |
| 5383148 | Single in-line memory module | James Testa, Edward H. Frank, Shawn Storm | 1995-01-17 |
| 5270964 | Single in-line memory module | Edward H. Frank, James Testa, Shawn Storm | 1993-12-14 |
| 5263139 | Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems | James Testa | 1993-11-16 |
| 5121487 | High speed bus with virtual memory data transfer capability using virtual address/data lines | — | 1992-06-09 |
| 5097483 | Tri-statable bus with apparatus to drive bus line to first level and then second level for predetermined time before turning off | — | 1992-03-17 |