Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11355348 | Integrated circuit, construction of integrated circuitry, and method of forming an array | Gurpreet Lugani, Kyle B. Campbell, Mario J. Di Cino, Aaron W. Freese, Kevin R. Shea | 2022-06-07 |
| 11321117 | Persistent multi-word compare-and-swap | Virendra J. Marathe, Matej Pavlovic, Timorthy L. Harris | 2022-05-03 |
| 11269839 | Authenticated key-value stores supporting partial state | Victor Cacciari Miraldo, Harold Carr, Maurice P. Herlihy, Mark S. Moir | 2022-03-08 |
| 11221891 | Generic concurrency restriction | David Dice | 2022-01-11 |
| 11216274 | Efficient lock-free multi-word compare-and-swap | Virendra J. Marathe, Mihail-Igor Zablotchi | 2022-01-04 |
| 11170816 | Reader bias based locking technique enabling high read concurrency for read-mostly workloads | David Dice | 2021-11-09 |
| 11068319 | Critical section speedup using help-enabled locks | Yosef Lev, Victor M. Luchangco, David Dice, Timothy L. Harris, Pantea Zardoshti | 2021-07-20 |
| 11056145 | Global secondary path locking technique enabling high read concurrency for read-mostly workloads | David Dice | 2021-07-06 |
| 11029995 | Hardware transactional memory-assisted flat combining | Yosef Lev | 2021-06-08 |
| 10949264 | Compact NUMA-aware locks | David Dice | 2021-03-16 |
| 10824424 | Efficient lock-free multi-word compare-and-swap | Virendra J. Marathe, Mihail-Igor Zablotchi | 2020-11-03 |
| 10811049 | Reader bias based locking technique enabling high read concurrency for read-mostly workloads | David Dice | 2020-10-20 |
| 10692727 | Integrated circuit, construction of integrated circuitry, and method of forming an array | Gurpreet Lugani, Kyle B. Campbell, Mario J. Di Cino, Aaron W. Freese, Kevin R. Shea | 2020-06-23 |
| 10678587 | Persistent multi-word compare-and-swap | Virendra J. Marathe, Matej Pavlovic, Timothy L. Harris | 2020-06-09 |
| 10565024 | Generic concurrency restriction | David Dice | 2020-02-18 |
| 10534538 | Fine-grained hardware transactional lock elision | David Dice, Virendra J. Marathe | 2020-01-14 |
| 10535368 | Reader bias based locking technique enabling high read concurrency for read-mostly workloads | David Dice | 2020-01-14 |
| 10521277 | Systems and methods for safely subscribing to locks using hardware extensions | David Dice, Timothy L. Harris, Yosef Lev, Mark S. Moir | 2019-12-31 |
| 10346196 | Techniques for enhancing progress for hardware transactional memory | David Dice, Maurice P. Herlihy | 2019-07-09 |
| 10152229 | Secure transaction interfaces | Daniel Peled, Offer Markovich, Tal Shalom Kol, Alon Muroch, Guy Stein | 2018-12-11 |
| 10127088 | Adaptive techniques for improving performance of hardware transactions on multi-socket machines | Victor M. Luchangco, Yosef Lev, Trevor J. Brown | 2018-11-13 |
| 10055129 | Read concurrency using hardware transactional lock elision | Yosef Lev | 2018-08-21 |
| 9785548 | Hardware extensions for memory reclamation for concurrent data structures | David Dice, Maurice P. Herlihy | 2017-10-10 |
| 9619281 | Systems and methods for adaptive integration of hardware and software lock elision techniques | David Dice, Yosef Lev, Timothy Merrifield, Mark S. Moir | 2017-04-11 |
| 9424080 | Systems and methods for utilizing futures for constructing scalable shared data structures | Maurice P. Herlihy | 2016-08-23 |