Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6593795 | Level adjustment circuit and data output circuit thereof | — | 2003-07-15 |
| 6459322 | Level adjustment circuit and data output circuit thereof | — | 2002-10-01 |
| 6337815 | Semiconductor memory device having redundant circuit | — | 2002-01-08 |
| 5510750 | Bias circuit for providing a stable output current | — | 1996-04-23 |
| 5369320 | Bootstrapped high-speed output buffer | Norihiko Satani | 1994-11-29 |
| 5357468 | Semiconductor memory device | Norihiko Satani, Yuichi Matsushita, Tetsuya Mitoma | 1994-10-18 |
| 5337278 | Low-power decoder for selecting redundant memory cells | — | 1994-08-09 |
| 5161121 | Random access memory including word line clamping circuits | — | 1992-11-03 |
| 5148399 | Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory | Junichi Suyama | 1992-09-15 |
| 5140556 | Semiconductor memory circuit having dummy cells connected to twisted bit lines | Masaru Uesugi | 1992-08-18 |
| 5103158 | Reference voltage generating circuit | Tsuneo Takano, Masaru Uesugi | 1992-04-07 |
| 5058073 | CMOS RAM having a complementary channel sense amplifier | Masaru Uesugi | 1991-10-15 |
| 5001669 | Semiconductor memory circuit having dummy cells connected to twisted bit lines | Masaru Uesugi | 1991-03-19 |