Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12216226 | Radar system | Cristian Pavao Moreira, Andreas Kollmann | 2025-02-04 |
| 12063045 | Feedback system monitoring | Jan-Peter Schat, Tim Lauber | 2024-08-13 |
| 11815553 | Duty cycle detector self-testing | Cristian Pavao Moreira, Andreas Kollmann | 2023-11-14 |
| 11817869 | System and method of controlling frequency of a digitally controlled oscillator with temperature compensation | Steffen Rode, Ralf Gero Pilaski | 2023-11-14 |
| 11689206 | Clock frequency monitoring for a phase-locked loop based design | Andreas Lentz | 2023-06-27 |
| 11658666 | Fractional-N ADPLL with reference dithering | Kai Hendrik Misselwitz | 2023-05-23 |
| 11218153 | Configurable built-in self-test for an all digital phase locked loop | Lars Henrik Heinbockel, Torsten Gerhardt, Christian Scherner | 2022-01-04 |
| 10826505 | All digital phase locked loop (ADPLL) with frequency locked loop | Andreas Kollmann, Christian Scherner | 2020-11-03 |
| 10778233 | Phase locked loop with phase and frequency lock detection | — | 2020-09-15 |
| 10396974 | Self-testing of a phase-locked loop using a pseudo-random noise | Jan-Peter Schat | 2019-08-27 |
| 10382045 | Digital phase locked loops | — | 2019-08-13 |
| 10187069 | Phase locked loop with lock/unlock detector | — | 2019-01-22 |
| 9893876 | Phase locked loop with reduced noise | — | 2018-02-13 |
| 9614536 | Phase locked loop with lock detector | — | 2017-04-04 |
| 9337850 | All-digital phase-locked loop (ADPLL) with reduced settling time | — | 2016-05-10 |
| 8462032 | Sigma delta modulator | Felix Naethe | 2013-06-11 |
| 7868949 | Circuit arrangement and method for locking onto and/or processing data, in particular audio, T[ele]v[ision] and/or video data | Andreas Szaj | 2011-01-11 |
| 7557623 | Circuit arrangement, in particular phase-locked loop, as well as corresponding method | Timo Giesselmann, Edwin Schapendonk, Frank Brand, Leendert van den Broeke | 2009-07-07 |
| 7221726 | Arrangement for generating a decoder clock signal | — | 2007-05-22 |