| 11074946 |
Temperature dependent voltage differential sense-amplifier |
Jainendra Singh, Jwalant Kumar Mishra |
2021-07-27 |
| 10685703 |
Transistor body bias control circuit for SRAM cells |
Jainendra Singh, Sushikha Jain, Deepti Saini, Jwalant Kumar Mishra |
2020-06-16 |
| 10679714 |
ROM cell with transistor body bias control circuit |
Jainendra Singh, Jwalant Kumar Mishra |
2020-06-09 |
| 10236071 |
Dual-bit ROM cell with virtual ground line and programmable metal track |
Rajat Kohli, Jwalant Kumar Mishra, Pankaj Agarwal |
2019-03-19 |
| 9691496 |
High density ROM cell with dual bit storage for high speed and low voltage |
Rajat Kohli, Jwalant Kumar Mishra, Pankaj Agarwal |
2017-06-27 |
| 9406374 |
Mitigating leakage in memory circuits |
Jainendra Singh, Pankaj Agarwal, Jwalant Kumar Mishra |
2016-08-02 |
| 9202588 |
1T compact ROM cell with dual bit storage for high speed and low voltage |
Rajat Kohli, Jwalant Kumar Mishra, Pankaj Agarwal |
2015-12-01 |
| 8139401 |
Integrated circuit with a memory matrix with a delay monitoring column |
Hendricus Joseph Maria Veendrick, Harold Gerardus Pieter Hendrikus Benten, Agnese A. M. Bargagli-Stoffi |
2012-03-20 |
| 7038936 |
Reading circuit for reading a memory cell |
Evert Seevinck, Alain Thijs, Maurits Mario Nicolaas Storms |
2006-05-02 |