RR

Roberto Rojas-Cessa

NT New Jersey Institute Of Technology: 11 patents #10 of 441Top 3%
PU Polytechnic University: 6 patents #4 of 69Top 6%
ED Empire Technology Development: 1 patents #283 of 547Top 55%
📍 Brooklyn, NY: #210 of 6,894 inventorsTop 4%
🗺 New York: #6,964 of 115,490 inventorsTop 7%
Overall (All Time): #220,244 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDate
11252630 Rail transit communication method and system Jianghua FENG, Mina Taheri, Qiang Fan, Nirwan Ansari, Mengchu Zhou +4 more 2022-02-15
11016516 Energy packet switches Haim Grebel, Zhengqi Jiang 2021-05-25
9577428 Packeted energy delivery system and methods Haim Grebel 2017-02-21
9501093 Measurement of clock skew between two remote hosts connected through computer networks Khondaker M. Salehin 2016-11-22
9392475 Determination of download throughput of wireless connection with compound probes Khondaker M. Salehin 2016-07-12
9118557 Measurement of packet processing time of end hosts through estimation of end link capacity Khondaker M. Salehin 2015-08-25
9100322 Forwarding cells of partitioned data through a three-stage Clos-network packet switch with memory at each stage Ziqian Dong 2015-08-04
8995456 Space-space-memory (SSM) Clos-network packet switch Chuan-Bi Lin, Ziqian Dong 2015-03-31
8861539 Replicating and switching multicast internet packets in routers using crosspoint memory shared by output ports Ziqian Dong 2014-10-14
8675673 Forwarding cells of partitioned data through a three-stage Clos-network packet switch with memory at each stage Zigian Dong 2014-03-18
8385231 Disseminating link state information to nodes of a network Nirwan Ansari, Zhen Qin 2013-02-26
8300650 Configuring a three-stage Clos-network packet switch Chuan-Bi Lin 2012-10-30
8274988 Forwarding data through a three-stage Clos-network packet switch with memory at each stage Ziqian Dong 2012-09-25
RE43466 Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined hierarchical arbitration scheme Eiji Oki, Hung-Hsiang Jonathan Chao 2012-06-12
RE43110 Pipelined maximal-sized matching cell dispatch scheduling Eiji Oki, Hung-Hsiang Jonathan Chao 2012-01-17
RE42600 Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme Eiji Oki, Hung-Hsiang Jonathan Chao 2011-08-09
7843908 Scalable two-stage Clos-networking switch and module-first matching Chuan-Bi Lin 2010-11-30
7046661 Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined hierarchical arbitration scheme Eiji Oki, Hung-Hsiang Jonathan Chao 2006-05-16
7006514 Pipelined maximal-sized matching cell dispatch scheduling Eiji Oki, Jonathan Chao Hung-Hsiang 2006-02-28
6940851 Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme Eiji Oki, Hung-Hsiang Jonathan Chao 2005-09-06