Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7782865 | Allocating VPI for user devices | Hiroyuki Kikuchi | 2010-08-24 |
| 6947427 | Transmission method and network system for accommodating a plurality of kinds of traffic in a common network | Motoo Nishihara, Kazuo Takagi | 2005-09-20 |
| 6934291 | ATM network system and method for allocating VPI for user devices | Hiroyuki Kikuchi | 2005-08-23 |
| 6496553 | PLL for reproducing standard clock from random time information | — | 2002-12-17 |
| 5864248 | Phase-locked loop circuit for reproducing clock signals synchronized with transmitter in receiver | — | 1999-01-26 |
| 5715286 | Digital phase synchronous circuit and data receiving circuit including the same | Masaaki Itoh | 1998-02-03 |
| 5694068 | Digital phase-locked loop (PLL) having multilevel phase comparators | — | 1997-12-02 |
| 5642357 | Transmission signal processing circuit which can determine an optimum stuff threshold value corresponding to a sort of a tributary unit of an input signal | Makoto Suzuki | 1997-06-24 |
| 5604774 | Fully secondary DPLL and destuffing circuit employing same | Masaaki Itoh | 1997-02-18 |
| 5144620 | Cross-connection network using time switch | Yasutoshi Ishizaki, Rikio Maruta, Hisashi Sakaguchi, Kuniyasu Hayashi | 1992-09-01 |
| 4935921 | Cross-connection network using time switch | Yasutoshi Ishizaki, Rikio Maruta, Hisashi Sakaguchi, Kuniyasu Hayashi | 1990-06-19 |
| 4803680 | Destuffing circuit with a digital phase-locked loop | Botaro Hirosaki | 1989-02-07 |
| 4727542 | Higher-order multiplex digital communication system with identification patterns specific to lower-order multiplex digital signals | Hiroshi Asano | 1988-02-23 |
| 4397017 | Stuff synchronization device with reduced sampling jitter | — | 1983-08-02 |