YE

Yoshimasa Endou

NE Nec: 2 patents #5,510 of 14,502Top 40%
📍 Rifu, JP: #1,001 of 2,101 inventorsTop 50%
Overall (All Time): #2,169,286 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
7050520 PLL (Phase-Locked Loop) circuit Hideyuki Asakawa 2006-05-23
6259274 Clock signal generator Katuhiko Kurosawa 2001-07-10