Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9343902 | Uninterruptible power supply apparatus and control method | — | 2016-05-17 |
| 8065645 | Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program | Shigeto Inui | 2011-11-22 |
| 7352067 | Stacked semiconductor device | Muneo Fukaishi, Hideaki Saito, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata | 2008-04-01 |
| 7330368 | Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections | Hideaki Saito, Muneo Fukaishi, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata | 2008-02-12 |
| 7236006 | Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program | Shigeto Inui | 2007-06-26 |
| 7221614 | Stacked semiconductor memory device | Hideaki Saito, Muneo Fukaishi, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata | 2007-05-22 |
| 7209376 | Stacked semiconductor memory device | Hideaki Saito, Muneo Fukaishi, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata | 2007-04-24 |
| 6918050 | Delay adjustment circuit and a clock generating circuit using the same | Atsushi Yoshikawa | 2005-07-12 |
| 6429688 | Semiconductor integrated circuit | — | 2002-08-06 |
| 6329844 | Semiconductor integrated circuit | — | 2001-12-11 |
| 6229340 | Semiconductor integrated circuit | — | 2001-05-08 |
| 5430668 | Floating point multiplier capable of easily performing a failure detection test | — | 1995-07-04 |
| 5426598 | Adder and multiplier circuit employing the same | — | 1995-06-20 |
| 5331581 | Artificial random-number pattern generating circuit | Chie Ohkubo | 1994-07-19 |
| 5231415 | Booth's multiplying circuit | — | 1993-07-27 |