Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8056036 | Semiconductor integrated circuit and method of designing thereof based on TPI | Toshiyuki Maeda | 2011-11-08 |
| 8015462 | Test circuit | Yoshiyuki Nakamura, Toshiyuki Maeda, Tomonori Sasaki | 2011-09-06 |
| 7681096 | Semiconductor integrated circuit, BIST circuit, design program of BIST circuit, design device of BIST circuit and test method of memory | Tomonori Sasaki, Yoshiyuki Nakamura | 2010-03-16 |
| 7613971 | Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit | — | 2009-11-03 |
| 6189128 | Design for testability method selectively employing two methods for forming scan paths in a circuit | — | 2001-02-13 |
| 6070258 | Logic synthesis for testability system which enables improvement in testability and effective selection of center state and logic synthesis method thereof | — | 2000-05-30 |
| 6028988 | System for logic synthesis-for-testability capable of improving testability for an FSM having an asynchronous reset state | — | 2000-02-22 |
| 5721690 | Logic circuit synthesis | — | 1998-02-24 |