Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5442206 | Lay-out structure of power source potential lines and grand potential lines for semiconductor integrated circuit | Takashi Ienaga | 1995-08-15 |
| 4882471 | Electronic equipment using a cover | — | 1989-11-21 |