Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6927450 | Non-volatile semiconductor storage device having a salicide structure | Teiichiro Nishizaka, Toshikatsu Jinbo | 2005-08-09 |
| 6788562 | Semiconductor memory device and write/readout controlling method error correction code decoding device | Teiichiro Nishizaka, Toshikatsu Jinbo | 2004-09-07 |
| 6396150 | Wiring structure of semiconductor device | — | 2002-05-28 |
| 6388932 | Memory with high speed reading operation using a switchable reference matrix ensuring charging speed | — | 2002-05-14 |
| 6347047 | Mask ROM semiconductor memory device capable of synchronizing the activation of the sense amplifier and of the word line | — | 2002-02-12 |
| 6310811 | Memory with high speed reading operation using a switchable reference matrix ensuring charging speed | — | 2001-10-30 |
| 6157580 | Semiconductor memory device capable of easily controlling a reference ratio regardless of change of a process parameter | — | 2000-12-05 |
| 5703820 | Semiconductor memory device with precharge time improved | — | 1997-12-30 |
| 5617355 | Semiconductor memory device having positive feedback sense amplifier | — | 1997-04-01 |
| 5565802 | Semiconductor device with differential amplifier operable at high speed | — | 1996-10-15 |
| 5528544 | Semiconductor memory device having high speed sense amplifier | — | 1996-06-18 |
| 5388071 | Semiconductor memory device regulable in access time after fabrication thereof | — | 1995-02-07 |
| 5303188 | Semiconductor memory device regulable in access time after fabrication thereof | — | 1994-04-12 |
| 5301144 | Semiconductor memory device having a decoding circuit for reducing electric field stress applied to memory cells | — | 1994-04-05 |
| 5295098 | Semiconductor memory device having high-speed three-state data output buffer circuit without voltage fluctuation on power voltage lines | — | 1994-03-15 |
| 5022003 | Semiconductor memory device | — | 1991-06-04 |