Sunao Torii has been granted 17 US patents while listed as an inventor at Nec . The first was granted in 1999 and the most recent in June 2021. Sunao Torii ranks #263,971 of 4,157,543 US inventors in our database (top 6.3%). Patent records list Sunao Torii in Tokyo, JP.
Patents per Year Patents granted per year, 1999 to 2021 Bar chart with a peak of 3 patents in 2005. peak 3 1999: 1 patents 1999 2000: 1 patents 2001: 1 patents 2001 2002: 1 patents 2005: 3 patents 2005 2007: 1 patents 2008: 1 patents 2008 2010: 1 patents 2011: 1 patents 2011 2012: 1 patents 2013: 2 patents 2013 2014: 2 patents 2021: 1 patents 2021
Issued Patents All Time
Showing 1–17 of 17 patents
Patent # Title Co-Inventors Date Approx Value ⓘ
11023021
Cooling system to minimize generation of bubbles inside flow passage by utilizing an auxiliary pump
Motoaki Saito
2021-06-01
8738881
Performance optimization system, method and program
Noriaki Suzuki , Junji Sakai
2014-05-27
8638665
Router, information processing device having said router, and packet routing method
Masamichi Takagi
2014-01-28
8531963
Semiconductor integrated circuit and filter control method
Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Masato Edahiro
2013-09-10
8412867
Semiconductor integrated circuit and filter and informational delivery method using same
Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Masato Edahiro
2013-04-02
8125364
Data compression/decompression method
—
2012-02-28
7911216
Semiconductor integrated circuit, debug/trace circuit and semiconductor integrated circuit operation observing method
Noriaki Suzuki
2011-03-22
7650453
Information processing apparatus having multiple processing units sharing multiple resources
—
2010-01-19
7418583
Data dependency detection using history table of entry number hashed from memory address
Atsufumi Shibayama , Satoshi Matsushita , Naoki Nishi
2008-08-26
7266643
Information processing device
—
2007-09-04
$60,000
6970997
PROCESSOR, MULTIPROCESSOR SYSTEM AND METHOD FOR SPECULATIVELY EXECUTING MEMORY OPERATIONS USING MEMORY TARGET ADDRESSES OF THE MEMORY OPERATIONS TO INDEX INTO A SPECULATIVE EXECUTION RESULT HISTORY STORAGE MEANS TO PREDICT THE OUTCOME OF THE MEMORY OPERATION
Atsufumi Shibayama , Satoshi Matsushita , Naoki Nishi
2005-11-29
$53,000
6961935
Multi-processor system executing a plurality of threads simultaneously and an execution method therefor
—
2005-11-01
$27,000
6931514
Data dependency detection using history table of entry number hashed from memory address
Atsufumi Shibayama , Satoshi Matsushita , Naoki Nishi
2005-08-16
$23,000
6389446
Multi-processor system executing a plurality of threads simultaneously and an execution method therefor
—
2002-05-14
$20,000
6330661
Reducing inherited logical to physical register mapping information between tasks in multithread system using register group identifier
—
2001-12-11
$22,000
6122712
Cache coherency controller of cache memory for maintaining data anti-dependence when threads are executed in parallel
—
2000-09-19
$79,000
5913059
Multi-processor system for inheriting contents of register from parent thread to child thread
—
1999-06-15
$31,000