ST

Sunao Torii

NE Nec: 16 patents #699 of 14,502Top 5%
EX Exascaler: 1 patents #2 of 2Top 100%
Overall (All Time): #272,791 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11023021 Cooling system to minimize generation of bubbles inside flow passage by utilizing an auxiliary pump Motoaki Saito 2021-06-01
8738881 Performance optimization system, method and program Noriaki Suzuki, Junji Sakai 2014-05-27
8638665 Router, information processing device having said router, and packet routing method Masamichi Takagi 2014-01-28
8531963 Semiconductor integrated circuit and filter control method Hiroaki Inoue, Masamichi Takagi, Masaki Uekubo, Masato Edahiro 2013-09-10
8412867 Semiconductor integrated circuit and filter and informational delivery method using same Hiroaki Inoue, Masamichi Takagi, Masaki Uekubo, Masato Edahiro 2013-04-02
8125364 Data compression/decompression method 2012-02-28
7911216 Semiconductor integrated circuit, debug/trace circuit and semiconductor integrated circuit operation observing method Noriaki Suzuki 2011-03-22
7650453 Information processing apparatus having multiple processing units sharing multiple resources 2010-01-19
7418583 Data dependency detection using history table of entry number hashed from memory address Atsufumi Shibayama, Satoshi Matsushita, Naoki Nishi 2008-08-26
7266643 Information processing device 2007-09-04
6970997 PROCESSOR, MULTIPROCESSOR SYSTEM AND METHOD FOR SPECULATIVELY EXECUTING MEMORY OPERATIONS USING MEMORY TARGET ADDRESSES OF THE MEMORY OPERATIONS TO INDEX INTO A SPECULATIVE EXECUTION RESULT HISTORY STORAGE MEANS TO PREDICT THE OUTCOME OF THE MEMORY OPERATION Atsufumi Shibayama, Satoshi Matsushita, Naoki Nishi 2005-11-29
6961935 Multi-processor system executing a plurality of threads simultaneously and an execution method therefor 2005-11-01
6931514 Data dependency detection using history table of entry number hashed from memory address Atsufumi Shibayama, Satoshi Matsushita, Naoki Nishi 2005-08-16
6389446 Multi-processor system executing a plurality of threads simultaneously and an execution method therefor 2002-05-14
6330661 Reducing inherited logical to physical register mapping information between tasks in multithread system using register group identifier 2001-12-11
6122712 Cache coherency controller of cache memory for maintaining data anti-dependence when threads are executed in parallel 2000-09-19
5913059 Multi-processor system for inheriting contents of register from parent thread to child thread 1999-06-15