Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11990901 | Semiconductor circuit and support device for logic circuit design | Yitao Ma, Tetsuo Endoh, Osamu Nomura, Li Tao | 2024-05-21 |
| 7617466 | Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device | — | 2009-11-10 |
| 7028273 | Delay optimization designing system and delay optimization designing method for a logic circuit and control program | Keisuke Kanamaru | 2006-04-11 |
| 6870199 | Semiconductor device having an electrode overlaps a short carrier lifetime region | Michio Nemoto, Takeshi Fujii | 2005-03-22 |
| 6243852 | Method of and an apparatus for logic circuit synthesis | — | 2001-06-05 |