Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8471336 | Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error | Hiroshi Furuta, Shouzou Uchida, Muneaki Matsushige | 2013-06-25 |
| 8169037 | Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error | Hiroshi Furuta, Shouzou Uchida, Muneaki Matsushige | 2012-05-01 |
| 8044694 | Semiconductor integrated circuit having latch circuit applied changeable capacitance and method thereof | — | 2011-10-25 |
| 7973371 | Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region | Hiroshi Furuta, Ichiro Mizuguchi | 2011-07-05 |
| 7808056 | Semiconductor integrated circuit device | Hiroshi Furuta, Shouzou Uchida, Muneaki Matsushige | 2010-10-05 |
| 7743289 | Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit | Hiroshi Furuta, Ichiro Mizuguchi | 2010-06-22 |
| 7688109 | Semiconductor memory device | Naoichi Kawaguchi | 2010-03-30 |
| 7274616 | Integrated circuit apparatus | Hiroshi Furuta, Kenjyu Shimogawa, Ichirou Mizuguchi, Shinji Takeda | 2007-09-25 |
| 5848023 | Semiconductor memory device operable in burst mode and method of controlling the same | Yoshiyuki Kato | 1998-12-08 |
| 5640358 | Burst transmission semiconductor memory device | — | 1997-06-17 |
| 5546410 | Semiconductor memory device with error self-correction system starting parity bit generation/error correction sequences only when increase of error rate is forecasted | Manabu Ando | 1996-08-13 |
| 5418748 | Bit line load circuit for semiconductor static RAM | — | 1995-05-23 |
| 5047984 | Internal synchronous static RAM | — | 1991-09-10 |