Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6351756 | Clock signal multiplier circuit for a clock signal generator circuit | — | 2002-02-26 |
| 5604775 | Digital phase locked loop having coarse and fine stepsize variable delay lines | Tetsuo Saitoh, Syuji Matsuo, Koichi Kitamura | 1997-02-18 |