Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6122653 | Block IIR processor utilizing divided ALU operation instructions | — | 2000-09-19 |
| 6119140 | Two-dimensional inverse discrete cosine transform circuit and microprocessor realizing the same and method of implementing 8.times.8 two-dimensional inverse discrete cosine transform | Eri Murata | 2000-09-12 |
| 5964824 | Two-dimensional IDCT circuit with input adder out output shifter for reducing addition operations during rounding-up | Eri Murata | 1999-10-12 |
| 5917736 | Two-dimensional inverse-discrete cosine transform circuit | Eri Murata | 1999-06-29 |
| 5768167 | Two-dimensional discrete cosine transformation circuit | — | 1998-06-16 |
| 5715017 | Motion estimating system | Yukihiro Naito, Takashi Miyazaki | 1998-02-03 |
| 5511207 | Program control circuit determining the designated number of times a sequence of instructions is repetitively executed to prevent further execution of a jump instruction | Yuko Ohde, Hideo Tanaka | 1996-04-23 |
| 5056004 | Program control system which simultaneously executes a program to be repeated and decrements repetition numbers | Yuko Ohde, Hideo Tanaka | 1991-10-08 |
| 4899301 | Signal processor for rapidly calculating a predetermined calculation a plurality of times to typically carrying out FFT or inverse FFT | Takao Nishitani, Yuichi Kawakami, Hideo Tanaka | 1990-02-06 |
| 4831575 | Apparatus for conversion between IEEE standard floating-point numbers and two's complement floating-point numbers | — | 1989-05-16 |
| 4817047 | Processing circuit capable of raising throughput of accumulation | Takao Nishitani, Hideo Tanaka, Kyosuke Sugishita | 1989-03-28 |
| 4723258 | Counter circuit | Hideo Tanaka | 1988-02-02 |
| 4722068 | Double precision multiplier | Takao Nishitani, Hideo Tanaka, Yuichi Kawakami | 1988-01-26 |
| 4571737 | Adaptive differential pulse code modulation decoding circuit | Takao Nishitani, Tadaharu Kato | 1986-02-18 |