Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8699585 | Transmitters for loop-back adaptive pre-emphasis data transmission | — | 2014-04-15 |
| 8050317 | Receiver with equalizer and method of operation | Shu Wang | 2011-11-01 |
| 7961830 | Clock and data recovery circuit having wide phase margin | Min-Bo Shin | 2011-06-14 |
| 7880521 | Differential driver and method capable of controlling slew rate | Byung-Hyun Lim | 2011-02-01 |
| 7697649 | Circuit for measuring an eye size of data, and method of measuring the eye size of data | — | 2010-04-13 |
| 7626523 | Deserializer, related method, and clock frequency divider | Min-Bo Shin, Sang-Jun Hwang | 2009-12-01 |
| 7583753 | Methods and transmitters for loop-back adaptive pre-emphasis data transmission | — | 2009-09-01 |
| 7499511 | Clock recovery systems and methods for adjusting phase offset according to data frequency | — | 2009-03-03 |
| 7456662 | Differential circuit, output buffer circuit and semiconductor integrated circuit for a multi-power system | — | 2008-11-25 |
| 6510549 | Method of designing a semiconductor integrated circuit device in a short time | — | 2003-01-21 |
| 6037637 | BiCMOS logical integrated circuit | — | 2000-03-14 |
| 5917342 | BiMOS integrated circuit | — | 1999-06-29 |
| 5771190 | Semiconductor static random access memory device having memory cells coupled to discharging line different in potential level to discharging line for write-in circuit | — | 1998-06-23 |
| 5739703 | BiCMOS logic gate | — | 1998-04-14 |
| 5670893 | BiCMOS logic circuit with bipolar base clamping | — | 1997-09-23 |
| 5619123 | Power supply circuit for non-threshold logic circuit | — | 1997-04-08 |
| 5604671 | Charge pump circuit for boosting voltage | — | 1997-02-18 |
| 5559451 | Bicmos push-pull type logic apparatus with voltage clamp circuit and clamp releasing circuit | — | 1996-09-24 |
| 5532500 | Semiconductor integrated circuit device having clock signal wiring construction for suppressing clock skew | Shin-ichi Ohkawa | 1996-07-02 |
| 5521541 | Semiconductor device capable of reducing a clock skew in a plurality of wiring pattern blocks | — | 1996-05-28 |
| 5473568 | Read write memory with negative feedback-controlled dummy memory circuit | — | 1995-12-05 |
| 5067003 | Semicustom-made semiconductor integrated circuit having interface circuit selectively coupled to different voltage source | — | 1991-11-19 |