Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12313640 | Validation device, validation method and non-transitory computer readable medium | Satoru Watanabe, Chihiro YASUI, Takeshi Yoshida | 2025-05-27 |
| 12222337 | Liquid chromatograph | Etsuho Kamata, Saki Yoshino | 2025-02-11 |
| 12085580 | Automatic suitability determination system | Satoru Watanabe, Takeshi Yoshida, Yuma OKABE, Chihiro YASUI | 2024-09-10 |
| 10416136 | Controlling apparatus | Shinji KANAZAWA | 2019-09-17 |
| 8330254 | Semiconductor device | Masayuki Furumiya, Hiroaki Ohkubo, Masayuki Mizuno, Koichi Nose, Yoshihiro Nakagawa +1 more | 2012-12-11 |
| 7282993 | Frequency characteristics-variable amplifying circuit and semiconductor integrated circuit device | — | 2007-10-16 |
| 6954111 | Voltage controlled oscillator having switches to adjust effective inductor lengths | Yoshinori Muramatsu | 2005-10-11 |
| 6833869 | Solid-state imaging device with voltage followers formed by selected row transistors and column transistors | — | 2004-12-21 |
| 6784932 | Hierarchical pixel readout multiplexer with switched capacitors for cancelling buffer offsets | — | 2004-08-31 |
| 6580063 | Solid state imaging device having high output signal pain | — | 2003-06-17 |
| 6410900 | Solid-state image sensor and method of driving the same | — | 2002-06-25 |
| 6313458 | Gain-adjustable photoreceiver circuit with photoelectric converter and amplifier | — | 2001-11-06 |
| 5546035 | Latch circuit having a logical operation function | — | 1996-08-13 |
| 5424968 | Priority encoder and floating-point adder-substractor | — | 1995-06-13 |
| 5369607 | Floating-point and fixed-point addition-subtraction assembly | — | 1994-11-29 |
| 5309385 | Vector division processing method and system | — | 1994-05-03 |
| 5303174 | Floating pointing arithmetic operation system | — | 1994-04-12 |
| 5084835 | Method and apparatus for absolute value summation and subtraction | — | 1992-01-28 |