ML

Marcello Lajolo

NA Nec Laboratories America: 3 patents #109 of 412Top 30%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
NE Nec: 1 patents #7,889 of 14,502Top 55%
📍 Princeton, NJ: #713 of 2,186 inventorsTop 35%
🗺 New Jersey: #16,490 of 69,400 inventorsTop 25%
Overall (All Time): #1,018,560 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
8219342 Variation tolerant network on chip (NoC) with self-calibrating links Simone Medardoni 2012-07-10
7784046 Automatically boosting the software content of system LSI designs Kanishka Lahiri, Srimat Chakradhar, Abhishek MITRA 2010-08-24
7702499 Systems and methods for performing software performance estimations Luciano Lavagno, Mihai Teodor Lazarescu, Alberto Sangiovanni-Vincentelli 2010-04-20
7502378 Flexible wrapper architecture for tiled networks on a chip Subhek Garg 2009-03-10
6880112 Method and apparatus for online detection and correction of faults affecting system-on-chip buses 2005-04-12