Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7149991 | Calibrating a wire load model for an integrated circuit | Wolfgang Roethig, Nader J. Haddad | 2006-12-12 |
| 6985843 | Cell modeling in the design of an integrated circuit | — | 2006-01-10 |
| 6487705 | Timing optimization and timing closure for integrated circuit models | Wolfgang Roethig | 2002-11-26 |