Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12298106 | Line of sight bias for missile guidance | Roberto Furfaro | 2025-05-13 |
| 8098655 | Systems and methods for converting a P packet/cycle datapath to a Q packet/cycle datapath | — | 2012-01-17 |
| 8014281 | Systems and methods for limiting the rates of data to/from a buffer | Raymond Marcelino Manese Lim, Song Zhang, Anurag P. Gupta | 2011-09-06 |
| 7936759 | Systems and methods for routing data in a network device | Kong Kritayakirana | 2011-05-03 |
| 7630309 | Systems and methods for limiting the rates of data to/from a buffer | Raymond Marcelino Manese Lim, Song Zhang, Anurag P. Gupta | 2009-12-08 |
| 7583663 | Systems and methods for converting a P packet/cycle datapath to a Q packet/cycle datapath | — | 2009-09-01 |
| 7167476 | Systems and methods for routing data in a network device | Kong Kritayakirana | 2007-01-23 |
| 7106696 | Systems and methods for limiting the rates of data to/from a buffer | Raymond Marcelino Manese Lim, Song Zhang, Anurag P. Gupta | 2006-09-12 |
| 7103038 | Systems and methods for converting a P packet/cycle datapath to a Q packet/cycle datapath | — | 2006-09-05 |
| 6970956 | Scaleable gap insertion in a data link | — | 2005-11-29 |
| 6952738 | Systems and methods for removing intrapacket gaps from streams of different bandwidths | — | 2005-10-04 |
| 6529571 | Method and apparatus for equalizing propagation delay | — | 2003-03-04 |
| 6480498 | High speed network switch bus clock | Vickie Pagnon | 2002-11-12 |
| 6421348 | High-speed network switch bus | Vickie Pagnon, Naveen Gopalakrishna | 2002-07-16 |
| 6285726 | 10/100 mb clock recovery architecture for switches, repeaters and multi-physical layer ports | — | 2001-09-04 |
| 6229469 | Adaptive differential ADC architecture | — | 2001-05-08 |
| 6154083 | Ground bounce control using DLL to optimize output stage di/dt using output driver replica | Kristen Luttinger | 2000-11-28 |
| 6121808 | DLL calibrated phase multiplexer and interpolator | — | 2000-09-19 |
| 6094082 | DLL calibrated switched current delay interpolator | — | 2000-07-25 |
| 6088415 | Apparatus and method to adaptively equalize duty cycle distortion | — | 2000-07-11 |
| 6037812 | Delay locked loop (DLL) based clock synthesis | — | 2000-03-14 |
| 6035409 | 1000 mb phase picker clock recovery architecture using interleaved phase detectors | — | 2000-03-07 |
| 6002717 | Method and apparatus for adaptive equalization using feedback indicative of undercompensation | — | 1999-12-14 |
| 5633606 | Scan flip-flop that holds state during shifting | Rajendran Sharma, Ronald Pasqualini | 1997-05-27 |