Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6442731 | Interactive method of optimum LSI layout including considering LSI chip size, test element groups, and alignment marks | — | 2002-08-27 |
| 5405466 | Method of manufacturing multilayer ceramic electronic component | Yasuyuki Naito, Yoshiki Hasegawa, Tadashi Morimoto, Yukio Tanaka | 1995-04-11 |
| 5219812 | Dielectric ceramic composition | Takuya Miyagawa, Yasuyuki Naito, Tadashi Morimoto | 1993-06-15 |