Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4784964 | EPI defect reduction using rapid thermal annealing | Mel Miller | 1988-11-15 |
| 4614021 | Pillar via process | — | 1986-09-30 |
| 4583282 | Process for self-aligned buried layer, field guard, and isolation | Carroll Casteel | 1986-04-22 |
| 4574469 | Process for self-aligned buried layer, channel-stop, and isolation | Sal Mastroianni, Carroll Casteel | 1986-03-11 |
| 4573257 | Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key | — | 1986-03-04 |
| 4423548 | Method for protecting a semiconductor device from radiation indirect failures | — | 1984-01-03 |