Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5995421 | Circuit and method for reading a memory cell | — | 1999-11-30 |
| 5708601 | Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device | Luigi Pascucci, Marco Maccarrone | 1998-01-13 |
| 5276653 | Fuse protection circuit | — | 1994-01-04 |
| 4331968 | Three layer floating gate memory transistor with erase gate over field oxide region | William M. Gosney | 1982-05-25 |
| 4301535 | Programmable read only memory integrated circuit with bit-check and deprogramming modes and methods for programming and testing said circuit | John K. Hampton | 1981-11-17 |
| 4290185 | Method of making an extremely low current load device for integrated circuit | Tsiu C. Chan | 1981-09-22 |
| 4281398 | Block redundancy for memory array | David L. Taylor | 1981-07-28 |
| 4251876 | Extremely low current load device for integrated circuit | Tsiu C. Chan | 1981-02-17 |