Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9537332 | Apparatus, system and method for charge balancing of individual batteries in a string of batteries using battery voltage and temperature, and detecting and preventing thermal runaway | Stephen D. Cotton, Brian Hanking, Cathy Snetsinger, Jason Toomey, Michael Carmel +2 more | 2017-01-03 |
| 8964451 | Memory cell system and method | — | 2015-02-24 |
| 7768238 | System and method for remote monitoring of battery condition | Charles B. Cotton, Ronnie Lim, Stephen D. Cotton, Michael Jump | 2010-08-03 |
| 7576517 | System and method for remote monitoring of battery condition | Charles B. Cotton, Ronnie Lim, Stephen D. Cotton, Michael Jump | 2009-08-18 |
| RE40423 | Multiport RAM with programmable data port configuration | Scott S. Nance, Nicholas J. Sawyer | 2008-07-08 |
| 7092279 | Shared bit line memory device and method | — | 2006-08-15 |
| 7050345 | Memory device and method with improved power and noise characteristics | — | 2006-05-23 |
| 5913223 | Low power set associative cache memory | William Lau | 1999-06-15 |
| 5715197 | Multiport RAM with programmable data port configuration | Scott S. Nance, Nicholas J. Sawyer | 1998-02-03 |
| 5682515 | Low power set associative cache memory with status inhibit of cache data output | William Lau | 1997-10-28 |
| 5124577 | Circuit for presetting the voltage of an output terminal | Harold L. Davis | 1992-06-23 |
| 4646306 | High-speed parity check circuit | Harold L. Davis | 1987-02-24 |
| 4495602 | Multi-bit read only memory circuit | — | 1985-01-22 |
| 4389705 | Semiconductor memory circuit with depletion data transfer transistor | — | 1983-06-21 |
| 4388702 | Multi-bit read only memory circuit | — | 1983-06-14 |
| 4388705 | Semiconductor memory circuit | — | 1983-06-14 |
| 4385369 | Semiconductor memory address buffer having power down mode | — | 1983-05-24 |