Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11824438 | Deadtime adjustment for a power converter | Robert J. Mayell, Yueming Wang, Roger Colbeck, Steven Greig Porter, Robert Busse +1 more | 2023-11-21 |
| 8754687 | Frequency-doubling delay locked loop | — | 2014-06-17 |
| 8587280 | Power factor correction converter control offset | Roger Colbeck, Anthony Reinberger | 2013-11-19 |
| 8582319 | Control arrangement for a resonant mode power converter | Anthony Reinberger | 2013-11-12 |
| 8558593 | Frequency-doubling delay locked loop | — | 2013-10-15 |
| 8508958 | LLC controller with programmable fractional burst frequency | Raymond Kenneth Orr, Hartley Fred Horwitz | 2013-08-13 |
| 8503250 | High speed DRAM architecture with uniform access latency | — | 2013-08-06 |
| 8283959 | Frequency-doubling delay locked loop | — | 2012-10-09 |
| 8274799 | Control arrangement for a resonant mode power converter | Anthony Reinberger | 2012-09-25 |
| 8248051 | Power factor correction converter control offset | Roger Colbeck, Anthony Reinberger | 2012-08-21 |
| 8102164 | Power factor correction converter control offset | Roger Colbeck, Anthony Reinberger | 2012-01-24 |
| 8045413 | High speed DRAM architecture with uniform access latency | — | 2011-10-25 |
| 8014172 | Control arrangement for a resonant mode power converter | Anthony Reinberger | 2011-09-06 |
| 7957211 | Method and apparatus for synchronization of row and column access operations | — | 2011-06-07 |
| 7848117 | Control arrangement for a resonant mode power converter | Anthony Reinberger | 2010-12-07 |
| 7817484 | Method and apparatus for synchronization of row and column access operations | — | 2010-10-19 |
| 7751262 | High speed DRAM architecture with uniform access latency | — | 2010-07-06 |
| 7746136 | Frequency-doubling delay locked loop | — | 2010-06-29 |
| 7643360 | Method and apparatus for synchronization of row and column access operations | — | 2010-01-05 |
| 7505336 | Method and apparatus for synchronization of row and column access operations | — | 2009-03-17 |
| 7456666 | Frequency-doubling delay locked loop | — | 2008-11-25 |
| 7450444 | High speed DRAM architecture with uniform access latency | — | 2008-11-11 |
| 7277334 | Method and apparatus for synchronization of row and column access operations | — | 2007-10-02 |
| 7269075 | Method and apparatus for simultaneous differential data sensing and capture in a high speed memory | — | 2007-09-11 |
| 7116141 | Frequency-doubling delay locked loop | — | 2006-10-03 |